摘要
为满足某雷达信号设计要求,文中基于国产小数锁相环芯片GM4704产生7.12-9.12 GHz的信号,采用传统的PLL方式产生,低相位噪声、低杂散的频率综合器。同时,给出了设计过程并对相关的设计参数进行分析,应用相关的PLL仿真软件对环路滤波器进行仿真设计,通过实际电路测试,相位噪声达到-97 d Bc/Hz@1 k Hz与理论计算较接近,杂散达到-70 d B。
In order to meet the design requirement of the radar signal,this article describe a frequency synthesizer based on the decimal phase locked loop chip GM4704 made in China. The conventional PLL technique is adopted to generate low phase noise signal from 7. 12 to 9. 12 GHz. The design process and the related design parameters are given. Also we use the PLL simulation to design the loop band filter. Circuit tests show that the phase noise can reach to- 97 d Bc / Hz@ 1 k Hz,which is close to the theoretical value; the spurious can reach- 71 d B.
出处
《电子科技》
2015年第7期54-55,59,共3页
Electronic Science and Technology
