期刊文献+

一种改进的控制流差错检测和恢复机制研究

Research on improved control flow error detection and recovery mechanism
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摘要 运行于处理器上的进程如果在运行期间发生暂态故障,有可能导致严重的系统故障或安全漏洞。因此,必须在对系统造成损害前检测并尽量纠正这些差错。现有的差错检测方法虽然潜在性能优异,但是成本极高,因此无法在实践中部署。为了解决这一问题,提出了一种基于硬件的控制流监控技术。该技术首先从程序二进制接口提取出程序的合法控制流图,计算出CRC签名,对合法的控制流图进行编码;然后,当程序在处理器上运行时,使用预先计算好的签名来检验程序的运行期间控制流。该技术的控制流差错检测覆盖率可达99.98%,且可快速纠正差错,提高了控制流暂态差错的容错性。它对主处理器的性能开销极低(1%左右),面积成本也比较小(<6%)。给出的控制流运行期间监控技术经过扩展后,可以高效地监控并检测出处理器上正在运行的指令的各种暂态差错。 Transient errors during execution of a process running on a processor can lead to serious system failures or security lapses. It is necessary to detect, and if possible, correct these errors before any damage is caused to the system. The existing error detection method is excellent potential performance, but high cost and hence cannot be deployed in practice. To solve this problem,this paper described a hardware based control flow monitoring technique, firstly, it extracted the valid control flow graph for the application from the application binary and computed the CRC signatures to encode the valid control flow graph. And then used these pre-computed signatures to verify the runtime control flow of the application while it executed on a processor. This technique achieves a high coverage of control flow error detection (99.98%) and has the capability to quickly recover from the error, making it resilient to transient control flow errors. It posed an extremely low performance overhead ( - 1% ) and reasonable area cost ( 〈 6% ) to the host processor. The framework for runtime monitoring of control flow described can be extended to efficiently monitor and detect any transient errors in the execution of instructions on a processor.
出处 《计算机应用研究》 CSCD 北大核心 2015年第8期2382-2386,共5页 Application Research of Computers
基金 国家自然科学基金重点资助项目(61321001/F01)
关键词 处理器 故障 控制流 检测 开销 processor failures control flow detection overhead
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参考文献15

  • 1王真,江建慧.基于概率转移矩阵的串行电路可靠度计算方法[J].电子学报,2009,37(2):241-247. 被引量:18
  • 2严鲁明,梁华国,黄正峰.基于时-空冗余的集成电路老化失效防护方法[J].电子测量与仪器学报,2013,27(1):38-44. 被引量:10
  • 3Alkhalifa Z, Nair V S S, Krishnamurthy N, et al. Design and evaluation of system-level checks for on-line control flow error detection [ J ]. I EEE Trans on Parallel and Distributed Systems, 2009,10 ( 6 ) : 627-641.
  • 4Li Aiguo, Hang Bingrong. On-line control flow error detection using re- lationship signatures among basic blocks[ J]. Computers & Electri- cal Engineering ,2010,36 ( 1 ) : 132-141.
  • 5Wolf J, Fechner B, Uhrig S,et al. Fine-grained timing and control flow error checking for hard real-time task execution [ C ]//Proc of the 7 th IEEE International Symposium on Industrial Embedded Systems. [ S. 1. 3 : IEEE Press,2012:257-266.
  • 6Vemu R, Abraham J A. Ceda: control-flow error detection using asser- tions[J]. IEEE Trans on Computers, 2011,60(9) :1233-1245.
  • 7Abadi M, Budiu M, Edingsson U, et al. Control-flow integrity princi- ples, implementations, and applications [ J]. ACM Trans on Infor- mation and System Security,2009,13( 1 ) :423-432.
  • 8Arora D, Ravi S, Raghunathan A, et al. Secure embedded processing through hardware-assisted run-time monitoring [ C ]//Proc of Confe- rence on Design, Automation and Test in Europe-Volume. [ S. 1. ] : IEEE Computer Society,2012 : 178-183.
  • 9Mao Shufu,Wolf T. Hardware support for secure processing in embedded systems[J]. IEEE Trans on Computers,2010,59(6) :84%854.
  • 10Ragel R G, Parameswaran S. A hybrid hardware-software technique to improve reliability in embedded processors [ J]. ACM Trans on Em- bedded Computing Systems,2011,10(3) :36-45.

二级参考文献33

  • 1Kim J S, Nicopoulos C, Vijakrishnan N, et al. A probabilistic model for soft-error rate estimation in combinational logic[A]. Proc. of the 1 st Int' l Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems, Pisa[C]. New York: Elsevier, 2034.25 - 31.
  • 2Asadi G, Tahoori M B. An analytical approach for soft error rate estimation in digital circuits[ A]. IEEE Int. Symp. on Circuits and Systems, Kobe [ C ]. Hoboken: John Wiley & Sons, 2005.2991 - 2994.
  • 3Krishnaswamy S, Viamontes G F, Markov I L, et al. Accurate reliability evaluation and enhancement via probabilistic transfer matrices[A]. Proc. of the Design, Automation and Test in Europe Conference and Exhibition, Munich[C ]. New York: ACM Society, 2005.282 - 287.
  • 4Parker K P and McCluskey E J. Probabilistic treatment of general combinational networks [J]. IEEE Trans on Computers, 1975,24(6) :668 - 670.
  • 5Parker K P and McCluskey E J. Analysis of logic circuits with faults using input signal probabilities[ J]. IEEE Trans on Computers, 1975,24(5) : 573 - 578.
  • 6Ogus R C. The probability of a correct output from a combinational circuit [ J ]. IEEE Trails on Computers, 1975,24 (5) : 534 - 544.
  • 7Zarandi H R, Miremadi S G, Ejlali A R. Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models[ A]. Proc. of the 18th IEEE Int'l Symp. on Defect and Fault-Tolerance in VLSI Systems, Boston[ C]. Washington De: IEEE Computer Society,2003.485 - 492.
  • 8Leveugle R., Cimonnet:D. ,Ammari A. System-Level Dependability Analysis with RT-Level Fault Injection Accuracy[ A]. 19th IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, Cannes, France, 2004 [ C ]. Los Alamitos, California: IEEE Computer Society,2004.451 - 458.
  • 9Koren I. Signal reliability of combinational and sequential circuits[A].Proc.of the 7th Int'l Symp. on Fault-Tolerant Computing,Los Angeles[C]. Washington DC: IEEE Computer Society, 1977.162 - 167.
  • 10Kwek K H and Tohma Y. Signal reliability evaluation of self-checking circuits[A] .Proc. of the 10th Int'l Syrup. on Fault- Tolerant Computing, Kyoto[C]. Washington DC: IEEE Computer Society, 1980.257 - 262.

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