一种高性能低功耗CMOS分频器电路设计

Circuit design of high-performance and low-power CMOS frequency divider

对低功耗CMOS数字系统设计中分频器电路设计问题,基于中芯国际0.18μm混合工艺,设计了一个基于真单相时钟结构的二分频单元,并通过将二分频单元多级串联实现26分频比的分频器电路。对电路的瞬态仿真结果表明:在500 MHz输入频率下,分频器可以分别实现2分频、4分频、8分频、16分频、32分频、64分频的信号输出,对应电路静态功耗为23.7μW。由于版图的电源线VDD、GND采用了双U型结构,避免了芯片面积浪费,每个二分频单元的版图面积仅为18×5.4μm2。基于版图的后仿真结果验证了该电路的功能正确性。

For low-power dissipation CMOS digital systems, frequency divider circuit is one of the most common basic circuits in digital system. With SMIC 0. 18 μm mixed signal technology, a two- frequency divider unit based on TSPC flip flop is designed and then a frequency divider circuit with 26 division ratio is made. The transient simulation results show that： frequency divider can realize the signal output respectively at the frequency division of 2, 4, 8, 16, 32 and 64 under 500 MHz input frequency. The static power consumption of the whole circuit is 23.7 μW. In layout design, the double U structure of power line VDD, GND helps to avoid the waste of chip area and the total area of the each frequency divider circuit is 18 × 5.5μ2. The post simulation from layout verifies the performance of the circuit.