一种多维网格编码译码器的高效FPGA设计

An Efficient FPGA Design of MDTCM Decoder

为在实时通信系统中有效利用多维网格编码调制(MDTCM)的短码特性,设计了一种适合FPGA实现的高效多维网格编码译码器。在该设计中,提出了一种易于硬件实现的改进归一化译码算法,采用四级流水线和乒乓环结构,并充分利用译码算法中的固有特性,有效降低了资源消耗和译码延迟。测试表明,该设计简单可靠,性能稳定,易于移植扩展,非常适合实时通信场合的应用,目前该译码器已成功应用于某实时通信系统中。

Aiming at the effectively-used the short-code characteristics of MDTCM in real-time communication system, an efficient design of MDTCM decoder is proposed. Based on this, a modified normalization decoding algorithm suitable for hardware implementation is designed. With four-pipeline and ping-pang loop structure, and by taking full advantage of the intrinsic characteristics of decoding algorithm, the re- source consumption and decoding delay are effectively reduced. Practical test show that this design, being simple, reliable and stable, and easy to transplant and extend, is suitable for real-time communication system, and now this decoder is successfully applied to certain real-time communication system.