一种低功耗指令Cache的设计与实现

Design and Implementation of a Low Power Instruction Cache

指令Cache的功耗主要源于Cache对数据存储器和标志存储器的访问.结合处理器的分支预测技术,利用处理器顺序执行指令时,对Cache标志存储器的空闲时间进行标志存储器预访问,能够在不降低Cache性能的同时,减少标志存储器和数据存储器的访问,降低Cache的功率消耗.提出了一种低功耗指令Cache的设计方法——BPPA,结合了处理器分支预测技术与Cache预防问技术来降低指令Cache的功耗.实现结果表明,与未使用BPPA技术的指令Cache相比,针对不同典型应用可以减少指令Cache功耗平均30%左右.

The main power consumption of instruction cache comes from the access to data memory and tag memory. Access to tag memory need only once per line during sequential execution. The branch prediction and Cache Pre- access can reduce the access to tag memory and data memory significantly. The method can reduce cache power while retaining its performance. A Branch Prediction and Cache Pre-access（BPPA） method is presented in this paper to reduce the cache power consumption. The power simulation result shows it can reduce about 30% power consumption with different applications.