一种面向超标量处理器的低功耗指令Cache设计

A Low-Power Instruction Cache Design for Superscalar Microprocessors

针对超标量结构中多体并行的流水化指令Cache提出了三种低功耗优化策略,首先是基于Cache路的条件放大技术,它根据标志匹配结果来关闭无关路中敏感放大器对存储阵列的驱动输出;其次是基于Cache行的动态电压调节技术,它只对当前访问的Cache行提供正常的操作电压,而其他Cache行都处于低电压休眠状态;最后是基于短循环程序的指令回收技术,它通过重复利用过期指令来减少对Cache的冗余访问.实验表明,这个低功耗设计在SPEC和PowerStone基准程序下可以将指令Cache的总功耗分别降低72.4%和84.3%,而处理器的IPC损失分别只有1.1%和0.8%,并且不会带来任何时序开销.

To reduce the power consumption, three optimization strategies are proposed for the multi-hank and pipelined instruction cache in superscalar. The first technique is conditional amplifying based on cache way, which avoids sense amplifiers driving data from memory arrays in irrelated ways. The second one is dynamic voltage sealing based on cache line, which provides the normal operation voltage just for the active cache line and keeps all the other cache lines drowsy in a lower voltage. The last strategy is instruction recycling based on short loop program, which reuses ancient instructions to prevent redundant cache access. Experimental results show that this design methodology can reduce the total power of instruction cache by 72. 4% and 84. 3% respectively in SPEC and PowerStone benchmarks, and bring processor IPC loss by only 1.1% and 0. 8% respectively, without any timing overhead.