小型CPT原子钟的数字电路优化研究

Optimization of Digital Circuits for Miniature CPT Atomic Clock

CPT原子钟是一种体积小、功耗低、指标优的新型原子钟。本文对小型CPT原子钟数字滤波算法开展优化研究,采用CIC滤波器前端滤波,低阶FIR滤波器后端滤波。新滤波模块在保证相同的噪声抑制比的情况下,节约逻辑资源,降低整钟功耗。基于以上方案实现的滤波模块,获得了55d B的滤波效果,同时节省了约42%的FPGA逻辑资源。

Coherent Population Trapping （CPT） atomic clock is a new type of atomic clock with low-power, small volume and excellent stability. In this paper, to optimize the digital filtering algorithm of miniature CPT atomic clock, we use Cascade Integrator Comb （CIC） filter as the front filter and low order FIR filter as the end filter. In the case of the same noise suppression radio, new filtering module has saved logic resources and reduced power consumption. Based on the above design, the filtering mod-ule reaches the filtering effect of 55dB and saves about 42% of FPGA logic resources.