VLIW DSP处理器下累加计算优化方法

Optimization Method for Accumulation Based on VLIW DSP Processor

当今VLIW DSP处理器拥有的指令种类越来越多,它们大多利用单一指令来完成一组复杂的计算,从而提高相关操作的执行效率.无论是在现有数字信号处理程序中,还是使用各种优化手段之后的程序代码中,累加计算在VLIW DSP处理器运算的程序中总是频繁出现,编译器如何自动高效地识别并合成处理器特有的累加指令就变得尤为重要.提出一种VLIW DSP处理器下累加计算优化方法,算法可以自动合成目标处理器的累加指令,充分利用处理器体系结构和资源的特点.最后在BWDSP处理器上实现本文的优化算法,实验结果表明,本算法有效减小了程序累加部分的汇编代码长度,从而提高了BWDSP对累加计算的处理能力.

Today,there are more and more kinds of specific instructions in VLIW DSP processor,which can be used to do a set of complex calculations. Cumulative calculation can be seen frequently in existing digital signal processing programs and the codes after optimization on VLIW DSP processor. How to identify and synthesize the specific accumulation instruction in compiler has becomes particularly important. This paper proposes an optimization method for accumulation based on VLIW DSP processor, which can synthesize the accumulation instruction to make full use of the architecture and resources of the target processor. Finally, the optimization method is implemented on the BWDSP processor with satisfactory. The results show that, this method can effectively reduce the length of the assembly code,thus it can enhance the processing ability of BWDSP for cumulative calculation.