HEVC运动估计模块的三维集成电路设计

3D IC Design for HEVC Motion Estimation Module

随着特征尺寸不断减小,芯片设计受到物理极限的挑战,基于硅通孔的三维集成电路逐渐成为研究热点.业界缺乏支持三维集成电路设计的EDA工具,为了克服这个困难,使用二维商业EDA工具,结合定制脚本,提出一套完整的三维集成电路设计流程,并使用此流程完成HEVC运动估计模块的三维集成电路设计.介绍了HEVC运动估计模块的三维电路结构划分,以及物理实现方法,包括布局布线、时钟树综合与时序验证.结果显示,三维HEVC运动估计电路相比其二维电路减小了75%占用面积,14.4%总线长,17.1%平均线长和12.3%功耗.

As feature sizes continue to shrink,IC design is faced with the challenges of physical limits.3DIC based on TSV gradually becomes a hot topic.There is scarcely EDA tool to support 3DIC design.In order to overcome this difficulty,2D commercial EDA tools are combined with custom scripts to form a complete 3DIC design flow.This flow is used to accomplish 3DIC design of HEVC motion estimation module.The 3Dcircuit partition and physical design of HEVC motion estimation circuit are introduced,including placement,routing,clock tree synthesis and timing verification.The results show that the 3DHEVC motion estimation circuit decreases 75% of footprint area,14.4% of total wire length,17.1% of average wire length and 12.3% of power consumption compared to 2Ddesign.