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基于高层LISA功耗模型的RISC处理器热量分析与仿真方法

Thermal Analysis and Simulation for RISC Processor Based on High-level LISA Power Model
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摘要 为了优化集成电路芯片的布局封装,提高芯片性能及可靠性,对处理器级别的实时片上温度调节技术进行评估,给出了一种实时计算芯片单元模块功耗和温度的仿真方法.采用高层LISA功耗模型,得到RISC处理器上通用应用程序的实时功耗;利用芯片后端设计软件Cadence Encounter对芯片进行布局规划设计,获得RISC处理器的floorplan信息;将实时功耗、floorplan信息及芯片规格参数作为输入信息,利用HotSpot热量分析工具,实现对RISC处理器快速低代价的热量分析仿真.实验结果表明,利用该方法可以准确分析芯片的热分布,获得反映芯片在实际运行过程中热量分布的数据,为优化集成电路芯片的布局封装、分析芯片性能及可靠性等提供最直接的温度信息. In order to optimize layout and packaging of IC chip,improve its performance and reliability and evaluate runtime regulation technology of operating temperature on processor-level,a real-time simulation method of calculating unit-based power consumption and runtime temperature is presented.By using high-level LISA power model,a runtime power consumption of generic applications on RISC processor is gained.Floorplan information about the RISC processor is obtained by Cadence Encounter software.HotSpot thermal analysis tool conducts fast,low-cost thermal analysis for RISC processor using the real-time power consumption,floorplan information and RISC chip′s specifications as input information.The experiment results show that the method can accurately analyze heat distribution of the RISC chips and obtains the temperature data which can reflect the heat distribution during actual operation.It provides the most direct temperature information for optimizing layout and packaging of IC chip,analyzing its performance and reliability,etc.
出处 《微电子学与计算机》 CSCD 北大核心 2015年第8期125-129,134,共6页 Microelectronics & Computer
基金 中科院长春光机所创新基金(Y2CX1SS125)
关键词 HOTSPOT 热量分析 LISA功耗模型 芯片floorplan HotSpot thermal analysis LISA power model chips floorplan
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参考文献13

  • 1Borkar St Design challenges of technology scaling [M].IEEE Micro, 1999 :23-29.
  • 2LALL P, PECHT M G, HAKIM E B.温度对微电子和系统可靠性的影响[M].贾颖,译.北京:国防工业出版社,2008.
  • 3Rabaey J M, Pedram M, et al. Low power designmethodologies[M]. New York: Kluwer academic pub-lishers Norwell, 1996.
  • 4http://lava. cs. Virginia. edu/HotSpot/.
  • 5Chattopadhyay A, Meyr H, Leupers R. LISA: A U-niform ADL for Embedded Processor Modeling, Im-plementation and Software Tool suite Generation[M].Morgan Kaufmann* 2008:95-130.
  • 6http : //eeweb. poly, edu/labs/nanovlsi/tutorials/soctu-torials/Tutorial—Encounter, html.
  • 7Huang W, Ghosh S,Velusamy S,et al. Hotspot: Acompact thermal modeling methodology for early-stagevlsi design[J]. IEEE Transactions on VLSL Systems,14(5):501-513,2006.
  • 8Kevin Skadron,Mircea R Stan, Wei Huang, et al.Temperature-aware microarchitecture : extended dis-cussion and results[C]// ISCA'03 Proceedings of the30th annual international symposium on Computer ar-chitecture. New York: ACM,2003.
  • 9Sankaranarayanan K,Velusamy S, Stan MR,et al. Acase for Thermal-Aware Floorplanning at the Microar-chitectural Level[J]. The Journal of Instruction-LevelParallelism, 2005.
  • 10Huang W,Stan M R, Scadron K, et al Con^)act thermalmodeling for temperature-aware design[C] //Proceedings ofthe 41st Design Automation Conference. 2004.

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