期刊文献+

多核处理器中改进的动态缓存优化技术

Improved Dynamic Cache Optimization Technology in Multicore Processor
下载PDF
导出
摘要 为提高多核处理器中缓存资源池效率并降低芯片总面积,设计三维多核结构,同时给出在线应用感知作业分配和缓存共享策略。通过分析应用程序性能特征预测资源需求量,将相邻层中具有不同缓存特点的作业分配给三维多核结构内核,使应用程序与缓存用途相匹配,同时根据应用程序对缓存需求度分配缓存资源,实现缓存资源利用率的最大化。实验结果表明,该策略可提高系统性能,降低能耗和芯片面积,与基于静态缓存的三维多核存储器相比,该三维多核结构的能量延迟乘积和能量延迟面积乘积分别提高了36.9%和57.2%。 In order to improve the efficiency of cache resource pool and reduce the total chip area in multicore processor,a 3D multicore structure is introduced.This structure implements a runtime application-aware job allocation and cache sharing policy.It improves energy efficiency in 3D multicore structure by providing flexible heterogeneity of cache resources and dynamically allocates job to cores of 3D multicore structure.It pairs applications with contrasting cache use,and partitions the cache resources based on the cache hungriness of the applications.Experimental results demonstrate that the proposed policy improves the system performance,reduces energy consumption and chip area.Compared with 3D multicore processor based on static cache,the proposed 3D structure improves system Energy-delay Product(EDP)and Energy-delay-area Product(EDAP)by up to 36.9% and 57.2%.
出处 《计算机工程》 CAS CSCD 北大核心 2015年第8期46-51,共6页 Computer Engineering
基金 河南省科技攻关计划基金资助项目(122102210430) 河南省教育厅科学技术研究基金资助重点项目(14B520036)
关键词 缓存资源池 缓存共享 多核处理器 三维多核结构 作业分配 cache resource pool cache sharing multicore processor 3D multicore structure job allocation
  • 相关文献

参考文献16

  • 1Loh G H. 3D-stacked Memory Architectures for Multi-core Processors [ C ]//Proceedings of the 35th International Symposium on Computer Architecture. Washington D. C., USA : IEEE Computer Society ,2008:453-464.
  • 2Coskun A K, Ayala J L, Atienza D, et al. Dynamic Thermal Management in 3D Multicore Architec-turesE C ]//Proceedings of Design, Automation & Test in Europe Conference & Exhibition. Washington D. C. , USA : IEEE Press ,2009 : 1410-1415.
  • 3Zhuravlev S, Blagodurov S, Fedorova A. Addressing Shared Resource Contention in Multicore Processors via Scheduling[ J]. ACM SIGARCH Computer Architecture News ,2010,38 ( 1 ) : 129-142.
  • 4Martinez J F, Ipek E. Dynamic Multicore Resource Management : A Machine Learning Approach [ J ]. IEEE Micro ,2009,29(5 ) :8-17.
  • 5汪玲,黄炎,袁光辉.重用感知的非一致缓存迁移策略研究[J].计算机工程,2014,40(2):81-85. 被引量:1
  • 6周本海,乔建忠,林树宽.基于多核处理器的动态共享缓存分配算法[J].东北大学学报(自然科学版),2011,32(1):44-47. 被引量:5
  • 7Varadarajan K,Nandy S K, Sharda V, et al. Molecular Caches: A Caching Structure for Dynamic Creation of Application-specific Heterogeneous Cache Regions [ C ]// Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. Washington D. C. ,USA: IEEE Computer Society ,2006:433-442.
  • 8Qureshi M K,Patt Y N. Utility-based Cache Partitioning:A Low-overhead, High-performance, Runtime Mechanism to Partition Shared Caches [ C ]//Proceedings of the 39th Annual IEEE/ACM International Symposium on Micro- architecture. Washington D. C., USA: IEEE Computer Society ,2006:423-432.
  • 9Kumar R, Zyuban V, Tullsen D M. Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads and Scaling [ C ]//Proceedings of the 32nd International Symposium on Computer Architecture. Washington D. C. , USA :IEEE Press ,2005:408-419.
  • 10Hijaz F, Shi Q, Khan O. Low-latency Mechanisms for Near-threshold Operation of Private Caches in Shared Memory Multicores [ C ]//Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops. Washington D. C. , USA: IEEE Computer Society ,2012:68-73.

二级参考文献21

  • 1Hill M D, Marry M R. Amdahl's law in the multicore era[J]. Computer, 2008,41 (7) : 33 -- 38.
  • 2Michaud R P. Replacement policies for shared caches on symmetric multicores:a programmer-centrie point of view[J ].IRISA, 2008,21( 1 ) :3 - 19.
  • 3Dybdahl H, Natvig L. A cache-partitioning aware replacement policy for chip multiprocessors[C]//Proceeding of 2006 ACM Conference on High Performance Computing. Bangalore: Springer, 2006:22 -34.
  • 4Qureshi M K, Patt Y N. Utility-based cache partitioning: a low-overhead, high performance runtime mechanism to partition shared cache[C]//Proceeding of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. Orlando: IEEE, 2006:423 -432.
  • 5Zhao L, lyer R, Upton M, et al. Hybrid last level caches for chip-multiprocessors [ J ]. ACM SIGARCH Computer Architecture, 2008,36 (2) : 56 - 63.
  • 6Lai S C, Lu S L, Stark J, et al. Cache misses for accurate data speculation and prefetching [ C ] // Proceeding of International Conference on Supercomputing. New York: ACM, 2002:189- 198.
  • 7Standard Performance Evaluation Corporation. SPEC CPU 2000[EB/OL]. [2007- 02-01]. http://www, spec. org.
  • 8Chang Jichuan, Sohi G S. Cooperative Caching for Chip Multiprocessors[J]. SIGARCH Computer Architecture News, 2006, 34(2): 264-276.
  • 9Bechmann B M, Marty M R, Wood D A. ASR: Adaptive Selective Replication for CMP Caches[C]//Proc. of the 39th Annual IEEE/ACM International Symposium on Microarchi- tecture. Orlando, USA: IEEE Computer Society, 2006: 443-454.
  • 10Reddy R, Petrov E Cache Partitioning for Energy-efficient and Interference-free Embedded Multitasking[J]. ACM Trans. on Embedded Computing Systems, 2010, 9(3): 1-35.

共引文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部