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5.12 Gbps高速抗辐照并串转换芯片的设计

The Design of a 5.12 Gbps high Speed,Radiation-tolerant Serializer ASIC
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摘要 本文介绍了一种用于粒子物理实验的抗辐照高速并串转换电路芯片的设计,重点介绍了SOS抗辐照工艺,并串转换电路的结构。实现了一款基于SOS 0.25um工艺的8位5.12Gbps并串转换芯片,测试得到芯片的总晃动(total jitter)=53.20ps,其中随机晃动(random jitter)=1.84ps,确定性晃动(deterministic jitter)=33.93ps。 A high speed, radiation - tolerant serializer developed for the particle physics experiment is introduced. This article focuses on the SOS radiation - tolerant process and the structure of the serializer. An 8 bits 5.12Gbps serializer based on the 0.25 um SOS process is realized and tested. The total jitter of the chip is 53.20ps, including the random jitter of 1.84ps and the deterministic jitter of 33.93ps.
出处 《核电子学与探测技术》 CAS 北大核心 2015年第5期443-447,共5页 Nuclear Electronics & Detection Technology
关键词 Silicon-On-Sapphire 并串转换 CML JITTER Silicon - On - Sapphire serialize CML jitter
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