基于FPGA的空间滤波测速算法实现

Spatial Filtering Velocity Measurement Method Based on FPGA

针对相关测速算法精度不高,实时性较差的问题,提出了一种基于FPGA的空间滤波测速方法。该方法以高速线阵CCD作为光电探测器,采用FPGA实现算法过程,各算法模块设计成并行流水型运算结构。实验结果表明测速系统能够实现优于0.5%的测速精度,1kHz的输出带宽,可以应用于高精度非接触测速领域。

The conventional correlating velocity measurement method takes a long time for calculation and its measurement accuracy is not very well. A spatial filtering velocity measurement method is proposed in this paper. It uses a CCD to detect the light intensity and a FPGA to process the sampled signal. The experimental result indicates that the velocity measure- ment accuracy is superior to 0. 5 % and can work with an output bandwidth of 1 kHz.