一种12位分段式电流舵DAC电路设计

Circuit design of 12-bit segmented current steering DAC

针对So C中DAC设计越来越受面积和功耗的制约,采用分段式结构,提出一种应用于So C模拟输出前端的12位100 MS/s电流舵型D/A转换器,其中高6位为温度计码,低6位为改进型Fibonacci数列,其减小了DAC的面积和毛刺。电路基于S MIC 0.13μm CMO S工艺,在1.2 V/3.3 V(数字/模拟)双电源供电下,满摆幅输出电流20 m A。在100 MHz采样频率、49.7 MHz输入信号下,无杂散动态范围(SFDR)达到89.448 d B,INL和DNL均小于0.5 LSB。

Since the design of DAC in SoC is more and more conditioned by area and power consumption, a 12-bit 100 MS/s current steering DAC applied to analog output front-end of SoC is proposed, in which a segmented architecture is employed. In this circuit, high 6-bit is thermometer code while low 6-bit is the improved Fibonacci Series which can cut down the area and glitch of DAC. Based upon SMIC 0.131μm CMOS process, the full-swing output current is 20 mA under the condition of 1.2 V/ 3.3 V dual power supply （digital and analog）. Simulation results show that both INL and DNL are all lower than 0.5 LSB, and the SFDR is up to 89.448 dB under the condition of 49.7 MHz input signal frequency at 100MHz sampling rate.