基于SDRAM大容量缓存FIFO控制器的设计与实现

Design and Realization of Big Capability Cache FIFO Controller Based on SDRAM

数据通过采集模块后需要进行缓存,然后再通过DMA写入上位机,SDRAM存储容量大,符合大批量数据的存储,FIFO可以在不同的速率下读写数据,根据两者的优势,本设计是基于SDRAM控制器实现的大容量缓存FIFO;系统中FPGA采用Altera公司的CycloneII:EP2C35F484I8,使用verilog语言实现,通过Quartus11.0编译、综合、布线后,时钟能够达到100 MHz;设计通过了仿真与验证,在仿真验证下,此大容量FIFO存储速率达到43.6 MByte/s;设计已经成功用于实际环境中,输入输出时钟完全不确定的情况下,SDRAM的最低利用率是43%,在时钟相差小的情况下,利用率可以达到100%,符合系统设计需要。

The data gathered through the module needs to be cached, after that it is written to the host machine. Based on the advantage of SDRAM having large capacity and FIFO can be written and read in any time and under any clock, it design the large capacity FIFO based on SDRAM. In the system, the type of FPGA is CyclonelI： EP2C35F48418 designed by ALTERA. It was realized through Verilog and com- piled, synthesized and fitterred by software Quartusll. 0, the clock can reached 100 MHz. The design is tested on FPGA, under verification and simulation, the rate of large storage FIFO can reached 43.6 MByte/s, the design is already applied in real system, under uncertain input clock and output clock, the minimum utilization of SDRAM is 43%, the maximum utilization is 100%, it can satisfy the system＇ s demand completely.