一种高电源抑制比的全MOS电压基准源设计

Design of a High Power Supply Rejection Ratio All MOSFET Bandgap Voltage Reference Source

基于MOS管在亚阈值区、线性区和饱和区的不同导电特性,采用TSMC 0.18μm CMOS工艺,设计了一种全MOS结构的电压基准源。为了改进核心电路,通过设计并优化预抑制电路,使整个电路实现了高电源电压抑制比的输出电压。对电路进行仿真,当电源电压大于1.5V时,电路进入正常工作状态;在1.8V电源电压下,-20℃~120℃范围内,温度系数为1.04×10^-5/℃,该电压基准源的输出电压为0.688 V;低频时,电源电压抑制比达到-159.3dB,在1MHz时电源电压抑制比为-66.8dB,功耗小于9.83μW。该电压基准源能应用于高电源电压抑制比、低功耗的LDO电路中。

A novel bandgap voltage reference source with all MOSFET structure was designed based on the different characteristics of the MOSFET sub-threshold region,linear region and saturated region. The circuit was implemented in TSMC CMOS 0.18 μm technology. The pre-rejection section of the circuit was designed to achieve a high power supply rejection ratio. With the Spectre simulator of the Cadence, simulation results showed that the proposed circuit could work normally while the supply voltage was more than 1.5 V. The output voltage of the voltage reference source was 0. 688 V, and the temperature coefficient was 1.04 × 10^-5/℃ in the range of -20 ℃ to 120℃ with the power supply voltage of 1.8 V. The circuit exhibited the PSRR of --159.3 dB at low frequency. The PSRR was - 66.8 dB and the power consumption was less than 9.83 μW at 1 MHz. The bandgap voltage reference source was suitable for the high PSRR arid low power LDO.