一种低相位噪声锁相环频率合成器的设计

Design of a Low Phase Noise PLL Frequency Synthesizer

通过MATLAB对锁相环进行系统建模与分析,采用改进型宽摆幅低噪声电荷泵结构,结合2位开关电容阵列技术与RC低通滤波技术,设计了一种低相位噪声锁相环频率合成器。基于SMIC 0.18μm CMOS工艺设计的芯片测试结果表明,该锁相环系统的频率覆盖范围达到1.27~1.82GHz;在中心频率为1.56GHz处的相位噪声为-105.13dBc/Hz@1 MHz,抖动（均方根）为2.2ps。

A low phase noise phase locked loop （PLL） frequency synthesizer was designed. Performances of the PLL system were analyzed through the systemic model built by MATLAB. The structure of charge pump with improved wide band and low noise, combined with 2 bit switch capacitor array and RC low pass filtering techniques was applied in this method. The results of the chip processed in SMIC 0. 18μm CMOS techniques showed that the frequency ranges of the PLL system was from 1.27 GHz to 1.82 GHz. The phase noise was -105.13 dBc/Hz@1 MHz and the RMS jitter was 2.2 ps at the center frequency of 1.56 GHz.