一种新的大容量SRAM编译器设计

Design of a New Large Capacity SRAM Compiler

介绍了一种大容量的SRAM编译器设计技术。根据SRAM容量和结构,提出了新的建模方案,并建立更优化的时序和功耗模型。同时,根据大容量SRAM在面积和性能上的需求,选择不同的译码器和拼接结构,采用合适的IP核进行拼接,并从结构上实现。对512kb和1 Mb的SRAM进行了流片测试,测试结果表明,该方案对于大容量的SRAM编译器设计是有效的。

A design of a new large capacity SRAM compiler was described. According to the capacity and structure of SRAM, a new modeling scheme was proposed and a more optimized model of sequence and power consumption was established. Also, according to the performance and area needs of large capacity SRAM, an appropriate IP core was selected to joint the SRAM with different decoders and structures. The 512 kb and 1Mb SRAMs had been taped out and tested. The test results showed that this design was effective for the large capacity SRAM compiler.