一种基于FPGA硬件求解函数的简化方法

A Method for Simplifying Process Mathematical Function in FPGA

本文研究了一种运用FPGA进行数据处理的方法,包括:提取输入数据的高log2M个比特位的数据,作为高有效位,根据预先设置的目标函数的计算表格,查找所述高有效位对应的目标函数值y(n)以及高有效位+1对应的目标函数值y(n+1);提取输入数据的剩余比特位数据,作为低有效位,并将所述低有效位与y(n)和y(n+1)的差值相乘,得到偏移值off(n),将该偏移值与所述高有效位对应的目标函数值y(n)相加,将计算结果作为所述输入数据对应的目标函数值。本方法具有控制简单、结构规则、单运算周期、计算精度较高的特点,适合于FPGA的数据处理实现。

In this paper, we study a kind of using FPGA for data processing method. It includes： extraction of the input data of high log2m bits of data, as high effective, according to a presetting the objective function calculation table, search the high effective bits that correspond to the objective function value y （n） and high effective add 1 bit corresponding to the objective function value Y （n ＋ 1）. Extracted from the input data the remaining bits of data, as low effective, and the effective bits and Y （n） and Y （n ＋ 1） of the difference between the obtained offset value off （n）, the offset value and the high effective of the objective function value Y （n） additive. The calculated results as the input data corresponding to the objective function value. This method has the advantages of simple control, structural rules, single operation cycle, and high accuracy. It is suitable for data processing of FPGA.