摘要
基于不规则部分并行结构设计了一种高吞吐量,低复杂度,码长码率可变且去除四环的低密度奇偶校验LDPC码及其译码结构实现方案,该编码结构可针对不同码长的不规则部分并行结构LDPC码进行扩展,译码器采用缩放最小和定点(Sum-Min)算法实现译码,中间信息节点存储器地址采用格雷码编码,降低动态功耗;采用Xilinx公司的Virtex-5XC5Vt X150T-ff1156FPGA芯片设计了一款码长1 270,码率1 2的不规则部分并行LDPC码的编码器和译码器。综合结果表明:该编码器信息吞吐量为2.52 Gb/s,译码器在10次迭代的情况下信息吞吐率达到44 Mb/s。
The low density parity check（LDPC）codes and the implementation scheme of the decoding structure were designed based on irregular semi- parallel structure. LDPC codes without four cycles have high throughput and low complexity,whose length and rate are variable. This coding structure can extend irregular semi- parallel LDPC codes with different code length. The decoder adopts Sum- Min algorithm to realize decoding. The memory address of middle information nodes applies Gray coding to reduce dynamic power consumption. Based on this structure,encoder and decoder of irregular semi-parallel LDPC codes were designed by using Xilinx Virtex-5 XC5 Vt X150T-ff1156 FPGA,whose code length is 1 270 bit and code rate is1 2.The comprehensive results show that the information throughput of this encoder can achieve 2.52 Gb/s and the information throughput rate of the decoder can reach 44 Mb/s in the case of 10 iterations.
出处
《现代电子技术》
北大核心
2015年第17期34-37,共4页
Modern Electronics Technique
