摘要
本文介绍了码率可配置Turbo译码器的FPGA设计与实现。可配置Turbo译码器可灵活支持1/3、1/6、1/10三种码率,减少了器件使用规模和资源,并支持固定迭代次数译码和动态迭代译码。码率可配置Turbo译码器最终在Xilinx公司的XC7K325T-2FFG900I芯片上实现。
In this paper, FPGA design and implement on code rate configurable Turbo Decoder are introduced. Configurable Turbo decoder supports three code rates： 1/3, 1/6, 1/10 flexibly which decreases the resource consume. Turbo decoder supports fixed iterative times and dynamic iterative times. Code rate configurable Turbo decoder has been implemented on the FPGA chip XC7K325T-2FFG900 I of Xilinx Company.
出处
《现代导航》
2015年第4期367-371,390,共6页
Modern Navigation
