GaAs场效应晶体管不同极性ESD损伤机理

Damage Mechanisms of Different Polarity ESD in GaAs Field Effect Transistor

对Ga As场效应晶体管(FET)进行3个正向和3个负向脉冲(3"+"3"-")、3个负脉冲(3"-")、3个正脉冲(3"+")3种极性静电放电(ESD)实验,不同极性ESD实验下器件的失效阈值不同。以栅源端对为例对实验结果进行分析,在3"+"3"-"和3"-"极性下,器件失效模式为栅源短路,在3"+"极性下器件电参数退化。运用热模型对ESD正负脉冲电压产生的温升进行了计算,器件的损伤机理为,在正向脉冲下为栅金属纵向电迁移导致肖特基势垒退化;在ESD负向脉冲下为高电场引起栅源端对击穿。

Ga As field effect transistors（ FETs） were carried out three positive and three negative pulses（ 3 ＂ ＋ ＂ 3 ＂- ＂）,three negative pulses（ 3 ＂- ＂）,and three positive pulses（ 3 ＂ ＋ ＂）electronic static discharge（ ESD） test,respectively. The results show that the failure thresholds of the device are different in different polarity ESD test. By analyzing the test results of the gate-source,failure mode of the device is gate-source short with 3 ＂ ＋ ＂3 ＂- ＂and 3 ＂- ＂ ESD,and electrical parameters of the device is degradation with 3 ＂＋ ＂ESD. The temperature rises of the device caused by ESD positive and negative pulses voltage were calculated quantificationally by thermal model. The damage mechanisms of the device were deterioration of the schottky barrier causing by gate metal electromigration with ESD positive pulse,and the breakdown of gate-source in high electric field with ESD negative pulse.