标准CMOS工艺下高速集成大光敏面光电探测器芯片的研制

Research on high-speed optical receiver with integrated large photosensitive surface photodetector based on standard CMOS process

为提高大纤芯(1 mm)塑料(POF)光纤通信用的单片集成光接收机(OEIC)的速率并降低成本,对Si基大光敏面光电探测器(PD)的结构、性能以及后续放大电路进行了研究。首先,基于标准CMOS工艺流程对N+/N-well/p-sub PD结构进行建模和优化设计,对其光谱响应曲线和频率特性曲线进行了仿真;其次,建立PD等效电路模型,结合设计的后续放大电路进行协同设计与仿真;最后,采用0.5μm CMOS工艺对单个面积为200μm×200μm的PD以及后续放大电路单片集成电路进行了流片、封装和测试。实验结果表明,在-2.5V偏压下和650nm波长入射光,N+/Nwell/p-sub PD的响应度约有0.12 A/W,暗电流约为-9pA;单片光接收机在小于10-9的误码率BER条件下,灵敏度为-23dBm,并得到250 Mbit/s速率的清晰眼图。

In order to improve the speed and lower the cost of the monolithic integrated optical receiver for large core（1mm）plastic optical fiber（POF）communication,the structure and performance of large photosensitive surface photodetector（PD）and subsequent amplifying circuit based on silicon are investigated.Firstly,based on the standard CMOS process,the model of N＋/N-well/P-sub PDs structure is established and optimized.The PD′s characteristics of optical spectral responsivity and frequency response are simulated.Then,the collaborative design and simulation are accomplished through combining the established PD′s equivalent circuit model with the designed subsequent amplifying circuit.Finally,by using the 0.5μm CMOS process,the single PD with size of 200μm×200μm,and the monolithic integrated circuit of PD and post amplifiers are packaged and tested,respectively.The tested results indicate that at the wavelength of 650 nm,the responsivity of N＋/N-well/p-sub PD is 0.12A/W,the dark current is about 9pA,under the bias voltage of-2.5V.The sensitivity of the monolithic integrated opticalreceiver is-23 dBm under the bit-error-rate（BER）of 10^-9.And a clear eye-diagram with the speed of250Mbit/s is achieved.The designed monolithic integrated optical receiver can be applied to 250Mbit/s optical fiber communication systems very well.