基于FPGA的Systolic乘法技术研究

Research on Systolic multiplication technology based on FPGA

Systolic乘法是一种基于SIMD-MC2模型的矩阵乘算法,无法直接应用在单独的嵌入式系统中,所以提出一种采用FPGA技术实现Systolic乘法的方法。该方法将FPGA的硬件并行特性与巧妙的并行算法结合起来,利用FPGA灵活可编程的特点,在FPGA内部设计了一种基于MC2模型的节点阵列来实现Systolic乘法。实际应用中,可以灵活地修改节点单元的数量和节点的功能来满足不同规模的运算矩阵需求并充分利用FPGA的资源。仿真结果验证了该方法的正确性。实际测试结果表明:该方法具有较快的速度和较高的实时性。

Systolic multiplication is an algorithm based on the SIMD-MC2 model, but plied in the embedded system directly. We propose an implementation of Systolic multi GA technology, which combines the hardware parallelism of the FPGA and the parall gether. To realize Systolic multiplication, we design a node array based on the MC2 mod it cannot be ap- plication by FP- el algorithm to- el inside the FP- GA by making use of the flexible and programmable features of the FPGA. In practical applications, the number and function of the nodes can be modified flexibly to meet the needs of different scale matrixes and the FPGA resources are fully utilized. Simulation results verify the proposed method, and the actual test results show that this method has a faster speed and a higher real-time performance.