基于FPGA的祖冲之序列密码算法实现

Realization of ZUC stream cipher based on FPGA

祖冲之序列密码算法是我国自主研发的运用于LTE网络中的国际标准密码算法,该算法包括祖冲之算法(ZUC)、加解密算法(128-EEA3)和完整性检测算法(128-EIA3)三个部分。目前,已有的对整个祖冲之序列密码算法特别是128-EEA3和128-EIA3的实现大多停留在理论。文中对ZUC算法模块、128-EEA3和128-EIA3做了硬件实现,整体设计在保持ZUC算法模块的高吞吐率的同时还可以和高速模块对接。最后,在Sparten-6 FPGA平台上对该设计进行了仿真和实现,并对其性能进行了比较和分析。

ZUC stream cipher is an international standard cryptographic algorithm of LTE network which is developed independently by our country. The three parts of the algorithm are ZUC algorithm, confidentiality algorithm （ 128-EEA3 ） and integrity algorithm （ 128-EIA3 ）. At present, the research of the algorithm is mostly theoretical study, especially confidentiality algorithm （128-EEA3） and integrity algorithm（128-EIA3）. This article presents a realization of ZUC stream cipher. The high throughput rate of ZUC algorithm remained in the whole design and a method of high speed interface is provided. Finally, the algorithm is simulated and realized on the Sparten-6 hardware platform, and the performance is compared and analyzed.