带分复用的三维片上网络测试规划研究

Research on test scheduling of three dimensional network-on-chip with bandwidth division multiplexing

三维片上网络(3D No C)中IP核的测试问题日趋突出,测试规划是提高测试效率的有效方法。基于重用No C作为测试存取机制的并行测试方法,针对IP核测试数据传输带宽与TAM带宽不匹配的问题,提出带分复用方法,对有限带宽的TAM进行动态细分,将多核的测试数据共享同一物理TAM实施并行传输,并结合3D No C结构设计二维编码,建立带宽分配和测试顺序模型,采用多种群遗传模拟退火算法,在总功耗、层功耗双重约束下对IP核的带宽分配和测试顺序进行双重优化,提高并行测试效率以获得最短测试时间。算法中针对测试顺序优化设计移位互换杂交策略,并运用精英配对方法加快种群寻优速度,设计求精操作进一步优化测试时间,通过比较、淘汰、替换机制加强种群间交流,增加种群多样性,避免算法陷入局部最优。以ITC'02标准电路作为测试对象,实验结果表明,该方法通过提高带宽利用率,提升了并行测试效率,降低了资源占用,有效地缩短了测试时间。

The IP core test problem in three dimensional network-on-Chip （3D NoC） has become more and more prominent; and test scheduling is an effective way to increase test efficiency. In this paper, based on the parallel test method with the NoC reuse as the test access mechanism, aiming at the mismatch problem between IP core test data transmission bandwidth and the bandwidth of test access mechanism in 3D NoC test, a bandwidth division multiplexing method is proposed. The limited band test access mechanism（TAM） is subdivided dynamically, the test data of multiple cores share the same physical TAM at the same time and are transmitted parallelly. Considering the 3D NoC structure, the two-dimensional coding is designed and the model of bandwidth allocation and test sequence is es- tablished. Under the dual constraints of total power and layer power consumptions, the multiple population genetic simulated annealing algorithm is adopted to perform the dual optimization of the bandwidth allocation and test sequence of IP cores, which improves the parallel test efficiency and achieves the shortest test time. Aiming at the test sequence optimization, the hybrid strategy of shifting and swapping is designed in the algorithm, and the strategy of elite pairing is used to improve the population optimization speed. And, the refinement operation is designed to further optimize the test time. With the mechanism of comparison, elimination and substitution, the exchange among populations is strengthened and the population diversity is increased, which makes the algorithm avoid falling into local optimum. Taking ITC＇02 standard circuit as the test object, experiment was conducted; and the experiment results show that through increasing the bandwidth usage rate, the proposed method improves the parallel test efficiency, reduces the resource consumption and effectively shortens the total test time.