基于FPGA的高速并行数据传输系统

High Speed Parallel Data Transmission System Based on FPGA

该系统以FPGA为核心,通过两个彼此独立的FPGA核心板构成高速并行数据传输系统的发送端和接收端。传输协议采用12bit有效数据带宽、5位循环冗余码进行校验编码(CRC),总线传输速率可达24Mbps以上。接收端成功接收完数据后可通过液晶屏显示数据内容,通过RS232总线上传至PC机进行分析,传输速率9600bps。传输过程中通过核心板上的LED指示灯指示传输线路状态。整个系统模块化程度好、集成度高,充分发挥单片机灵活实用的特点和运算速度快的优势。

This system takes FPGA as the core ,while the sender and the receiver of high‐speed parallel data transmis‐sion system have been constituted by two independent FPGA core boards .Transfer protocol adopts 12 bit effective data bandwidth and five cyclic redundancy check code（CRC） ,and transmission rate of bus can reach more than 24 megabits per second .The receiver can be displayed panel data content by LCD after successfully receiving the data which is analyzed by uploading to the PC through the RS232 bus with the transmission rate 9600 BPS .The state of transmission lines is indicated through the LED indicator light on the core board in the process of transmission .The whole system with good modular de‐gree and high integration plays full advantage of flexible and fast practical computing speed .