摘要
设计了一种应用于8位100 MHz采样频率流水线ADC的采样保持电路。采用电容翻转的主体结构及下级板采样技术,设计了使用共源共栅密勒补偿的两级运放。在不影响性能的前提下提出对传统栅压自举采样开关的改进方案,减小了栅压自举开关的面积。该采样保持电路采用CSMC0.18μm CMOS工艺,1.8 V电源电压进行设计。Spectre仿真并使用Matlab分析输出动态特性表明,电路达到了74.7 d B的无杂散动态范围(SFDR),信纳比(SINAD)为60.8 d B。
A sample and hold circuit for 8 bit 100 MSPS pipelined ADCs is presented. A two stage amplifier with cascade miller compensation for the capacitor flip around architecture and bottom plane sampling technique is used. The traditional bootstrapped switch is improved to reduce the area without impacting performance. The circuit is based on CSMC 0.18 pm CMOS process and simulated by Spectre. Dynamic parameters are analyzed with Matlab, which shows the SFDR is 74.7 dB and SINAD is 60.8 dB.
出处
《电子与封装》
2015年第9期29-32,共4页
Electronics & Packaging
关键词
采样保持
栅压自举
流水线ADC
sample and hold
bootstrapped switch
pipelined ADCs
