高精度低功耗Sigma-Delta调制器的设计

Design of a High Resolution Low Power Sigma-Delta Modulator

设计了一种应用于音频和传感领域的高精度低功耗的Sigma-Delta调制器。该调制器采用四阶单环一位的CRFF结构,通过开关电容型全差分电路的使用,减小了偶次谐波、衬底以及电源噪声,以及斩波技术的使用,降低了直流失调和低频噪声,达到了提高精度和降低功耗的目的。本设计采用Global foundries 0.18μm CMOS工艺,电源电压为1.8 V,过采样率为128,采样时钟频率为5.12 MHz。仿真结果表明,该调制器信噪比达100.2 d B,整个调制器的功耗仅为380μW。

A Sigma-Delta modulator applied in the audio and sensor is proposed in this paper. The proposed modulator is implemented in the single loop forth order one bit CRFF structure. A fully differential switch capacitor circuit is used to reduce the even order distortions and the noises from substrate and power, and chopping is applied to reduce the offset and the 1/f noise, to improved the precision and reduce the power consumption. The whole circuit is based on the Global foundries 0. 18 μm CMOS technology with a supply voltage of 1.8 V, an OSR of 128, and a sampling frequency of 5.12 MHz. Simulation results show that SNR of the modulator can reach 100. 2 dB, while the power dissipation is merely 380 μW.