基于FPGA的32位片上网络设计与验证

Design and Verification of FPGA-based 32-bits Network-on-Chip

基于Stanford-No C模型设计实现了采用虚拟通道技术和虫孔交换策略的片上网络路由器。为输入缓冲队列结构路由器采用XY路由算法和信约(credit-based)机制实现数据微片的流控制,其虚拟通道和开关分配采用分离式输入优先分配,round-robin仲裁机制解决资源竞争问题。基于该路由器建立了32位数据位宽的4×4 2D MESH结构No C模型。仿真和测试结果表明,该片上网络占用资源少,最大工作频率为139 MHz,节点间最大吞吐率为4.46 Gbps。

The virtual-channel and wormhole-switching NoC router is designed based on Stanford-NoC model. The NoC router is input-queued architecture, using XY routing algorithm and credit-based flow control mechanism to manage the data flow. Separable input-first allocator with round-robin arbitration is adopted in the allocation of virtual channels and crossbar switch. A 32-bit data width 4＆#215;4 2D MESH NoC has been realized and implemented on the FPGA development platform. Results show that this NoC prototype takes a small amount of FPGA resources. The maximum frequency is 139 MHz and the maximum throughput between routers is up to 4.46 Gbps.