期刊文献+

锁相环技术在变速率PDH传输中的应用

Application of phase locked loop technique in variable data rate PDH transmission
下载PDF
导出
摘要 采用了基于统计预测的时钟锁相环技术,介绍了该技术的设计方案和实现原理,通过FIFO的满空程度控制电荷泵输出相应的电平信号,利用该电平信号控制VCXO的输出时钟,使接收端恢复的时钟频率与数据保持同步,且抖动小。 The paper uses the phase locked loop technique based on statistical prediction, introduces the de- sign scheme and implementation principle of the technology, through the full degree of FIFO to control the charge pump output corresponding level signal, the signal is made use of controlling the output of the VCXO clock, to restore the receiver clock frequency and data in sync, and the jitter is small.
作者 吴松
出处 《光通信技术》 北大核心 2015年第10期47-48,共2页 Optical Communication Technology
关键词 统计预测 锁相环 PDH传输 时钟恢复 statistical prediction, phase locked loop, PDH transmission, clock recovery
  • 相关文献

参考文献4

二级参考文献30

  • 1Mozhgan Mansuri, Chih-Kong Ken Yang. Jitter optimization based on phase-locked loop design parameters[J]. IEEE Journal of Solid-State Circuits. 1998, 37(11): 1375-1382.
  • 2Ali Hajimiri, Thomas H. Lee. A General Theory of Phase Noise in Electrical Oscillators[J]. IEEE Journal of Solid-State Circuits. 1998, 33(2): 179-194.
  • 3Kenneth S. Kundert. Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers [EB/OL]. July 2005. http://www.designers-guide.org/.
  • 4Soliman S, Yuan F, Raahcrnifar K. An overview of design techniques for CMOS phase detectors[C]. IEEE International Symposium on Circuits and Systems 2002. ISCAS 2002, 5: 457-460.
  • 5Lee J, Razavi B. Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits[J]. IEEE Journal of Solid-State Circuits. 2004, 39(9): 1723-1732.
  • 6Juarez-Hernandez E, Diaz-Sanchez A. A novel CMOS charge pump circuit with positive feedback for PLL applications[C]. The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, 1: 349-352.
  • 7Dean Banerjee. PLL Performance, Simulation and Design[M]. Oxford University Press, 2003.
  • 8Maneatis, J. G. Low-jitter process-independent DLL and PLL based on self-biasedtechniques[J]. IEEE Journal of Solid- State Circuits. 1996. 31(11): 1723-1732.
  • 9Lee Tai-Cheng, Razavi Behazad. A stabilization technique for phase-locked loop[J]. IEEE Journal of Sol- id-state Circuits, 2003, 38(6): 888-894.
  • 10Juarez-Hernandez E, Diaz-Sanchez A. A novel CMOS charge pump circuit with positive feedback for PLL applications [C]. in Proc Int Conf Electron, Circuits Sys, 2001, 1:349-352.

共引文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部