摘要
为实现对高速中频数字信号的降频、降速和滤波,得到低速零中频的数字基带信号,利用Matlab的Simulink工具箱中的DSP Builder的高级模块库设计模型系统,在模型系统中加入时钟频率和通道数等顶级设计约束脚本,设计优化流水线的RTL系统。给出Matlab与Modelsim仿真的结果分析以及综合、布局布线后的占用资源的对比,仿真结果表明了该系统设计方案和参数设置的正确性与实时性。
To realize frequency deducing,velocity deducing and filtering for high-speed digital signals of IF and obtain a low rate baseband signal of zero-IF.Using advanced blocksets of DSP builder in Simulink toolboxes of Matlab,the module system was designed.Top scripts were added in model system to generate the RTL to optimize the pipeline,such as the clock frequency and the number of channels.The simulation results of Matlab and Modelsim were analyzed and comparison results of the use of resources after placement and routing were presented.The simulation results show the correctness and the real-time property of the design and parameter settings.
出处
《计算机工程与设计》
北大核心
2015年第10期2695-2699,共5页
Computer Engineering and Design
