标准单元电路-版图设计自动优化技术

Technique of the Circuit-Layout Design Automation Optimization for the Standard Cell

提出了一种标准单元的电路-版图设计自动优化技术。根据目标电学性能等确定电路中器件的参数值,然后根据参数变化微调现有的标准单元版图,快速自动生成符合设计规则的新版图。该技术可从新版图中获取电路寄生参数,对电路的电学性能进行评估,进一步提高电路-版图设计自动优化速度。测试表明,该技术既可以用于加速标准单元建库和设计移植,也可以支持对更高层的SOC设计进行延时和功耗的在位优化,加速设计收敛,可缩短开发周期。

The technique of the circuit-layout design automation optimization for the standard cell was proposed. The new parameter values for each device were re-calculated based on the difference of the circuit performance and the design specification,then the new layout for the updated circuit design from the previous standard cell layout design with the leverage of standard cell layout tuning techniques was automatically generated. In the automatic optimization technology,the accurate parasitic parameters were extracted from the new layout,and the electrical properties of the circuit were evaluated with the parasitic effects taken into account. The speed of the circuit-layout design automation optimization was improved. The test results show that this technique can speed up the standard cell library development and the design migration,and also support the on-site design optimization for SOC timing and power dissipation with fast design closure by tuning the standard cell device parameters. So the development cycle can be shorten.