版图邻近效应的高精度标准单元波动检测电路

High-Precision Standard Cell Variation Measurement Circuit for Layout Proximity Effect

随着集成电路的发展,工艺尺寸进一步微缩,工艺波动导致的器件波动对电路性能以及可靠性的影响越来越严重。版图邻近效应就是先进工艺下影响工艺波动的重要因素。为了应对先进工艺下版图邻近效应(LPE)的影响,代工厂需要确立器件波动最小且最优标准单元版图。如何精确测量相同标准单元的不同版图的器件波动具有很大的挑战。提出了一个高分辨率、高速且测试便利的器件波动检测电路,用来对6种优化LPE引入的器件波动影响的标准单元版图进行测试。电路在28 nm工艺上进行了流片验证,电路面积为690μm×350μm,并对全晶圆进行了测试。通过分析NMOS和PMOS的测试结果,对比了不同版图形式应对LPE影响的效果,进而为代工厂设计和优化标准单元版图,尽可能减小LPE引入的器件波动提供参考。

With the development of the integrated circuit（ IC）,feature size has shrunk step by step,thus the impacts of device variation induced by process variation on the performance and reliability of IC are more and more serious. Layout proximity effect（ LPE） is one of the most important problems that affect process variation. In order to balance the influence of LPE,IC foundries need to set up a standard cell library with the optimal layout environment that suppresses device variation most. It is a great challenge to accurately measure the device variations of the same standard cells in different layouts.A high-precision,high-speed and easily measurable device variation monitor was proposed to measure the threshold voltage variation of 6 standard cell layouts for optimization of device variation induced by LPE.The measurement circuit was taped out in 28 nm technology with an area of 690 μm × 350 μm. The measurement was carried out on the whole wafer. By analyzing the variation results of NMOS and PMOS,the effects of different standard cell layouts on suppressing the influence of LPE were compared. The experiment provided a reference for the IC foundry in standard cell layout design and optimization and suppressing the influence of process variation induced by LPE effects.