期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

一种改善三栅分栅快闪存储器耐久性能的方法

A Method of Improving the Endurance for Triple Split Gate Flash Memory
下载PDF
导出
摘要 基于三栅分栅闪存在擦除操作F-N隧穿停止时界面电场恒定的特性,提出一种动态擦除电压模型,该模型基于稳定循环操作后浮栅电位的理念,通过实时可监测的浮栅电位值来动态调节闪存器件擦除操作的工作电压,提升了三栅分栅闪存器件的耐久特性。从实际监测数据可以看出,为保持稳定的浮栅电位,浮栅擦除操作电压随着编程/擦除循环次数先快速增加,并在循环10 000次后逐渐趋于饱和。相对于传统的恒擦除电压方式,通过这种新的动态擦除电压方式,器件在经过100 000次循环编程/擦除后阈值电压的漂移从原始1.2 V降低为小于0.4 V,优化了器件耐久性的工作窗口约0.8 V。 A dynamic erasing voltage model was proposed based on character of the constant interface electric field of triple split gate flash memory as F-N tunneling erasing stops. Based on stabilizing the potential of floating gate after the cycle operation,the erasing voltage of flash memory can be dynamically adjusted by real-time monitoring its threshold voltage, thus the endurance performance was improved for triple split gate flash. The actual monitoring results show that,in order to keep a stable potential of floa-ting gate,the erasing voltage increased steeply as the increasing times of programming / erasing circulation,and saturate gradually after 10 000 cycles. Comparing to constant erasing voltage method,the threshold voltage shift of this dynamic erasing voltage model was reduced from 1. 2 V to less than0. 4 V after 100 000 programming / erasing cycles,which gain the endurance about 0. 8 V.
作者 曹子贵 戴敏洁 高超 黄浩 王卉 程凯
机构地区 上海华虹宏力半导体制造有限公司
出处 《半导体技术》 CAS CSCD 北大核心 2015年第10期759-763,774,共6页 Semiconductor Technology
基金 上海市青年科技启明星计划(B类)(14QB1402200)
关键词 闪存储器 三栅分栅 F-N隧穿 耐久性 动态 擦除电压 flash memory triple split gate Fowler-Nordheim（F-N） tunneling endurance dynamic erasing voltage
分类号 TP333 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献19

  • 1VERMA G,MIELKE N.Reliability performance of ETOX based flash memories[C]∥Proceedings of the26thIEEE International Reliability Physics Symposium.1988:158-166.
  • 2TKACHEV Y,LIU X,KOTOV A,et al.Observations of single electron trapping/detrapping events in tunnel oxide of Super FlashTMmemory cell[C]∥Proceedings of IEEE Non-Volatile Memory Technology Symposium.2004:45-50.
  • 3LIU X,MARKOV V,KOTOV A,et al.Endurance characteristics of Super Flashmemory[C]∥Proceedings of the 8thIEEE International Conference on So lid-state and Integrated Circuit Technology.2006:763-765.
  • 4HORI T,IWASAKI H.Excellent charge-trapping pro perties of ultrathin reoxidized nitrided oxides prepared by rapid thermal processing[J].IEEE Electron Device Letters,1988,9(4):168-170.
  • 5HWANG H,TING W,KWONG D L,et al.Electrical and reliability characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal processing in N2O[C]∥Proceedings of the 8thIEEE International Conference on Solid-State and Integrated Circuit Technology Electron Devices Meeting.1990:421-424.
  • 6USHIYAMA M,KATO M,ADACHI T,et al.Highly reliable N2O-oxynitrided tunnel oxides for flash memory[C]∥Proceedings of the 8thIEEE International Conference on Solid-State and Integrated Circuit Technology.Yokohama,Japan,1994:23-26.
  • 7JONG F C,HUANG T Y,CHAO T S,et al.Improved flash cell performance by N2O annealing of interpoly oxide[J].IEEE Electron Device Letters,1997,18(7):343-345.
  • 8KIOOTWIJK J H,KRAHEHBURG H.van WOERLEE P H,et al.Deposited inter-poly-silicon dielectrics for nonvolatile memories[J].IEEE Trans action Electron Devices,1999,46(7):1435.
  • 9OKADA Y,TOBIN P J,REID K G,et al.Gate oxynitride grown in nitric oxide(NO)[C]∥Proceedings of the IEEE VLSI Technology.Honolulu,HI,USA,1994:105-106.
  • 10KAO D B,MC J P,NIX W D,et al.Two-dimensional silicon oxidation experiments and theory[C]∥Proceedings of the IEEE Electron Devices Meeting.1985,31:388-391.

二级参考文献18

  • 1Van Houdt J, Wellekens D, Haspeslagh L. The HIMOS flash technology: the alternative solution for low-cost embedded memory. Proc IEEE, 2003, 9:627.
  • 2Kynett V, Fandrich M, Anderson J, et al. A 90-ns one-million erase/program cycle 1-Mbit flash memory. IEEE J Solid-State Circuits, 1989, 24:1259.
  • 3Liu X, Markov V, Kotov A, et al. Endurance characteristics of SuperFlash^R memory. IEEE 8th International Conference on Solid-State and Integrated Circuit Technology, 2006:763.
  • 4Wellekens D, van Houdt J, Faraone L, et al. Write/erase degradation in source side injection flash EEPROM's: characterization techniques and wear-out mechanisms. IEEE Trans Electron Devices, 1995, 42:1992.
  • 5Wu T I, Chih Y D, Chen S H, et al. Characterization of split gate flash memory endurance degradation mechanism. IEEE Proceedings of 11th IPFA, 2004:115.
  • 6Hu L C, Kang A C, Chen E, et al. Gate stress effect on low temperature data retention characteristics of split-gate flash memoties. Microelectron Reliab, 2005, 45:1331.
  • 7Hu L C, Kang A C, Wu T Y, et al. Efficient low-temperature data retention lifetime prediction for split gate flash memories using a voltage acceleration methodology. IEEE Trans Device Mater Reliab, 2006, 6:528.
  • 8Hu L C, Kang A C, Tai I, et al. Statistical modeling for post-cycling data retention of split-gate flash memories. 42th Annual International Reliability Physics Symposium, 2004:643.
  • 9Hu L C, Kang A C, Shih J R, et al. Statistical modeling for post- cycling data retention of split-gate flash memories. IEEE Trans Device Mater Reliab, 2006, 6:60.
  • 10Van Houdt J, Heremans P, Deferm L, et al. Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications. IEEE Trans Electron Devices, 1992, 39:1150.

共引文献1

半导体技术
2015年 第10期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部