一种基于In-Situ AVS技术的低功耗处理器实现方法

A Low Power Implememtation Method on Processor Based on In-Situ AVS Technique

为了进一步降低ARM Cortex M0处理器的功耗,提出了一种基于In-Situ AVS(Adaptive Voltage Scaling)技术的低功耗电路实现方法.该方法通过电路的路径延时估算出监测窗口大小(ΔT)和电压调整的错误(pre-error)数量阈值(nlimit),将部分关键路径的触发器替换成实时延时检测电路,对重要的几条路径的延时和错误进行实时监测,经AVS控制单元和电压调整模块随着PVTA的变化自适应地调整电压,有效地降低电路功耗.在SMIC 180nm工艺下设计了一款ARM Cortex M0处理器,将此方法应用于处理器的一个关键模块,即AHB到APB的桥接电路(AHB_to_APB).测试结果表明,在一个观测区间(N=1 000)内错误率为8.9E-4时,电路功耗降低了28%.

In order to excessively reduce power dissipation of the ARM Cortex M0 processor, we propose a Low power implememtation circiut based on In-Situ AVS Technique. The main process is to estimate the monitoring window（△T） and pre-error limit number（nlimit ） which detelmings the voltage adjusting through the path delay of the circuit. Besides, the In-Situ Delay Monitor replaces the flip-flops at the end of critical paths. After detecting the path delay and pre-error using the In-Situ Delay Monitor, the circuit voltage could be adaptively adjusted through the AVS control unit and voltage regulator with the varying of PVTA, which is an efficient scheme to tune the supply voltage of digital circuits according to variations. We have designed a Arm Cortex M0 processor in the SMIC 180 ns process, and applied this method to a critical module（AHB to APB bridge）. As a result, We simulated the power dissipation, and find that the circuit applied AVS technique has reduced 28~ with the pre-error rate of 8. 9E-4 during a observation interval compared to the design former.