一种高性能14位采样保持电路

A High Performance 14 Bit Sample and Hold Circuit

设计了一种应用于流水线型模数转换器的14位100MHz采样保持电路,并在电路设计中,提出了一种改进型的栅压自举采样开关电路。在不增加电路复杂性的情况下,栅压自举采样开关电路可以有效地增加采样开关管的开启时间和关断时间,以及电路的可靠性。采样保持电路采用电容翻转式结构,以及采用增益提高的全差分折叠式共源共栅跨导放大器来实现。采用SMIC1.8V/3.3V0.18μm 1P6M CMOS工艺对电路进行设计与仿真。仿真结果显示,在10.009765MHz输入信号,100 MHz工作频率下,输出信号的无杂散动态范围(SFDR)为95.9dB,与传统自举开关相比,提高了16.3dB。

A 14 bit 100 MHz sample and hold（S/H） circuit for pipelined A/D converter was designed. An improved bootstrapped switch was presented to accelerate the turn on and turn off processes and improve the reliability, without increasing design complexity. The S/H circuit was based on capacitor flip-around S/H architecture with gain-boosted fully differential folded cascode operational transconductance amplifier. The entire S/H circuit was designed and simulated in SMIC 1.8 V/3.3 V 0.18 μm 1P6M CMOS process. Simulation results showed that the spurious free dynamic range（SFDR） of the proposed S/H circuit achieved 95.6 dB, which was about more 16.3 dB over the S/H circuit based on the conventional bootstrapped switch.