GMR-1 3G中LDPC高速编码器的设计与实现

Design and Implementation of LDPC Code High Speed Encoder in the GMR-1 3G

针对GMR-1 3G标准中的LDPC码,设计实现了一种多码长、多码率的编码器,采用并行处理的方式,降低了编码的时延,提高了编码的速率。使用Quartus II工具进行功能仿真,验证了编码的正确性和有效性。

According to the LDPC encoder ofGMR- 130 standard, a new design scheme for the common LDPC encoder of mul- ti-rate, multi-length based on FPGA is proposed. This encoder has realized universal LDPC code encoder, reduced the delay of encoding and improved the efficiency of encoder by using parallel structure. The software of Quartus II is used to do the synthesis simulation.Through simulation and experiment, the correctness and validity of this encoder are testified.