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基于FPGA的BGA焊点健康管理原理与实现 被引量:2

Theory and Implementation of BGA Solder Joint Health Management Based on FPGA
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摘要 针对BGA封装的FPGA焊点故障频发、现有的检测手段非常有限的问题,提出了一种基于FPGA的BGA焊点失效监测模型及实现方法;从制造生产因素和环境应力两方面对FPGA的BGA焊点失效因素进行了分析;建立失效检测模型,首先根据欧姆定律确定了检测原理,接着基于IPC7095B确定了焊点易失效区域,最终依据电容充放电时间与端电压的关系确定了检测方法;通过逻辑编码和基于Xilinx公司V5系列FPGA的实现,表明该方法可用于对FPGA的BGA焊点健康信息的管理,并根据不同的检测标准对检测情况进行了比较。 For FPGA BGA package solder joint failures occur frequently, the existing detection means very limited, presents a FPGA-- based BGA solder joint failure monitoring Models and Methods; analyzed the FPGA's BGA solder joint failure factors from manufacturing and environmental stress ; establish failure detection model, first determine the detection principle according to Ohm's law and IPC7095B, according to the relationship between capacitor charging and discharging time and the terminal voltage to determine the detection method; by logic coding and V5 series based on Xilinx Inc. FPGA implementations show that this method can be used to manage the FPGA BGA solder joint health information, and according to different testing standards for testing situation compared.
机构地区 中航工业计算所
出处 《计算机测量与控制》 2015年第10期3310-3312,共3页 Computer Measurement &Control
基金 航空科学基金(20101931005)
关键词 BGA FPGA 焊点 健康管理 BGA FPGA solder joint health management
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  • 1梁凯,姚高尚,简虎,熊腊森.微电子封装无铅钎焊的可靠性研究[J].电焊机,2006,36(5):18-21. 被引量:6
  • 2IPC美国电子工业联接协会.IPCLJEDEC J-STD-033潮湿,回流敏感性SMD的处理、包装、装运和使用标准[S].1999.
  • 3BHATIA A, HOFMEISTER J P, JUDKINS J, et al. Advanced testing and prognostic of ball grid array components with a stand-alone monitor IC [J] . IEEE Instrumentation and Measurement Magazine, 2010, 9 (10) : 42 -47.
  • 4SCHNETKER T R. In-situ monitoring and method to determine accumulated printed wiring board thermal and/ or vibration stress fatigue using a mirroed monitor chip and continuity circuit: USA, US7648847 [P] . 2010.
  • 5FILHO W C M, BRIZOUX M, FREMONT H, et al. Improved physical understanding of intermittent failure in continuous monitoring method [J] . Microelectronic Reliability, 2006 (46): 1886-1891.
  • 6HOFMEISTER J P, SPUHLER P, MOILANEN M. Method and resistive bridge ciecuit for the detection of solder-joint failures in a digital electronic package: USA, UST19694B2 [P] . 2007.
  • 7Matos J, et al. A boundary scan test controller for hierarchical BIST [A]. Proc. Inter. Test Con. [C]. 1992, 217-223.
  • 8Ferreira J, Gericota M, Ramalho J, eta. BIST for 1119. 1- Compatible Boards: A Low-Cost and Maximum-Flexibility Solu tion [A]. Proc. International Test Conference. 1993 [C]. pp. 536-543.
  • 9Haberl O F, Kropf T. A Chip Solution to hierarchical and boundary scan compatible board level BIST [A], Proc, Great Lakes Symposium on VLSI [C].1992, 16-21
  • 10Harrison S, Noeninckx G, Horwod P, et al, Hierachical boundaryscan. a scan chip-set solution [A], Proe, International Test Conference [C]. 2001, 480-486

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