面向ASCRA的循环流水启动间距自动分析及优化

Automatic Analysis and Optimization about Initiation Interval for Loop Pipeline in ASCRA

在实现循环到流水硬件结构自动映射过程中,迭代间启动间距的自动分析技术是可重构编译器研究的难点.在现有细粒度可重构编译器中,主要采用人工输入制导语句的方法来控制循环并行流水硬件结构自动映射所需启动间距信息的生成,该方法只能采用固定启动间距方式对流水硬件结构进行控制,不能充分发挥并行流水硬件结构的性能,同时人工确定启动间距的方法降低了可重构计算应用的部署效率.针对细粒度可重构编译器的现状,文中提出了一种面向ASCRA的循环流水启动间距自动分析及优化方法.在细粒度可重构编译器中,建立多层循环流水迭代间启动间距分析模型,提出非固定启动间距控制策略,采用自动生成算法得到迭代间启动间距向量信息,并采用流水线调度技术对迭代间启动间距进行优化.实验结果表明,与现有HLS工具相比,文中方法不仅能够提高可重构计算应用在异构加速平台上的部署效率,同时能够有效改善循环应用在FPGA协处理器中流水执行时的性能,具有一定的可行性.

The autonomous analysis technology about the Initiation Intervals（IIs）between iterations of loop,is a difficulty in the research of reconfigurable compilers,when the loop is mapping to a pipelined hardware circuit.The existing fine-grained reconfigurable compilers mainly adopt the guided statements to control the generation of IIs between iterations of loop for pipelined hardware circuit.This method has not reduced the performance of hardware circuit because of the fixed IIs,but guided statements has also affected the deployment efficiency of reconfigurable systems due to the difficulty sure of the IIs.In this paper,an automatic analysis and optimization method about Initiation Interval（IIs）for loop pipeline in ASCRA is proposed to improve the existing reconfigurable compilers.Through modeling the pipelined IIs between iterations of loop and automatically analysis algorithm,the IIs vector between iterations of loop can be acquired.In addition,this paper proposed an optimization algorithm about IIs to improve the performance of loops.The experiment data shows that this method can improve the efficiency of auto-mapping in reconfigurable compilers,and improve the performance of pipelined hardware circuit generated by reconfigurable compiler.The feasibility of this method can be proved.