SRAM型FPGA的SEU容错技术研究

Study on the SEU-tolerant Techniques for SRAM-based FPGAs

在空间辐射环境下,SRAM型FPGA比ASIC器件更容易产生单粒子翻转(SEU)效应,造成器件逻辑错误和系统故障,因此对航天应用中的SRAM型FPGA必须采取相应的抗单粒子翻转设计措施,提高FPGA空间应用的可靠性。分析了SEU产生原因及国内外针对SEU效应提出的FPGA加固设计方法,重点分析介绍了三模冗余技术、刷新回读技术和局部动态可重构技术等加固技术,总结比较了各种技术的优缺点。

Under the space radiation, the SRAM-based FPGA is more susceptible to single event upsets （ SEU ） than ASIC devices. Due to errors induced by SEU, the function of the SRAM-based FPGA might be interrupted, even broken down. The SEU-tolerant methods are designed to improve the reliability of the SRAM-based FPGA on space applications. This paper reviews the reason of SEU and several SEU-tolerant methods for FPGA harden design, main- ly focus on the triple modular redundancy （ TMR ） method, the scrubbing and readback method and the FPGA dy- namic partial reconfiguration technology.