KASUMI算法的芯片设计与实现

Design and Implementation of KASUMI Algorithm in Chip

KASUMI算法是第三代移动通信系统(3G)使用的一种加密算法.提出一种二合一结构来实现KASUMI算法的芯片设计,依据此二合一结构,KASUMI算法由原始的八轮循环迭代减少为四轮,从而降低了时钟周期数,提高了吞吐率.同时,该设计还实现了f8加密和f9完整性验证两种模式.基于SMIC 0.13μm CMOS工艺的综合结果表明,KASUMI算法的时钟频率为123.4MHz,面积为13 979门,吞吐率为1.97Gb/s,与其他同类方法相比,提高了23%.

KASUMI algorithm is an encryption algorithm used in the third generation mobile communication system（3G）.In this paper,we propose a two-in-one architecture to complete the design of KASUMI algorithm in chip.Based on the architecture,the iteration of the loop in KASUMI algorithm reduces from original 8rounds to 4rounds.Therefore,the number of clock cycles of the design is reduced and the throughput is improved.Additionally,the design still implements the encryption of f8 mode and the integrity verification of f9 mode.Using SMIC 0.13μm CMOS technology,clock frequency of this design and the count of the gates are 123.4 MHz and13979 gates respectively.Most importantly,the throughput achieves 1.97 Gbps,which is 23% faster than previous results.