高吞吐率LDPC码编译码器的FPGA实现

High-throughput LDPC Coder and Decoder FPGA Implementation

新兴的60GHz无线通信标准IEEE 802.11ad在采用单载波调制方案时,最高传输速率可达到4.62Gb/s,最高处理速率为1.76GHz.标准中,采用准循环低密度奇偶校验码(QC-LDPC)以保证高传输速率下较低的误码率.针对该标准,设计并实现了高吞吐率的LDPC编译码器.编码器用移位寄存器作为基本单元实现.与此同时,对比了生成矩阵的不同存储方式以优化编码结构.译码算法选用改进的最小和算法,译码器的硬件结构兼容4种码率,并拥有3种调制方法的接口.按照设计结构,用Verilog硬件描述语言实现了LDPC编译码器,并得到了正确的仿真结果.同时,在V7-485tFPGA上完成综合,分析逻辑资源消耗.结果,当FPGA时钟频率为150 MHz时,传输速率可达到1.26Gb/s.

IEEE 802.11 ad is an emerging 60 GHz wireless communication standard.The maximum transfer rate is4.62Gb/s,and the maximum processing rate is 1.76 GHz,when using single carrier modulation schemes.The standard use a quasi-cyclic LDPC code（QC-LDPC）in order to ensure a low error rate at a high transfer rate.For the standard,this paper designs high-throughput LDPC coder and decoder.Implementation of the encoder use shiftregister as the basic unit.At the same time,compared to the different storage methods of generation matrix,paper optimizes the coding structure.Decoding algorithm select modified minimum sum algorithms.Decoder hardware architecture is compatible with four kinds of bit rates,and has three kinds of modulation method interface.In accordance with the design of the structure,paper implements LDPC coder and decoder with the Verilog hardware description language,and get the correct simulation results.It completes the comprehensive and analyses logic resource consumption on V7-485 t FPGA.As a result,when the FPGA clock frequency is 200 MHz,the transmission rate is up to 1.68Gb/s.