基于可控功耗的扫描分段测试结构

Scan segmentation test architecture for power controllability

随着芯片尺寸进入微纳米级时代,集成电路测试过程中产生的功耗也越来越大,已经成为了芯片生产和测试的瓶颈。已有的研究主要是降低移位功耗或者捕获功耗,但是很少有方法能够同时降低这2个阶段的功耗,而且目前还没有针对捕获功耗可控性的研究。该文提出了一种基于可控功耗的扫描分段结构,该结构能够控制移位阶段和捕获阶段的功耗,并且只需增加很小的面积开销。同时还设计了一种高效的电路结构分析算法来检测触发器之间的依赖关系,以及一种能够直接降低同一时刻触发器跳变的扫描分段策略,这种策略通过不断的迭代分段组合来完成最优分组。该分段方法是第一个基于电路结构依赖和时钟树影响的功耗可控方法。实验表明,该结构在ISCAS89和IWLS2005基准电路测试中都有明显的效果。

As chip sizes reach micro-nano levels,the increasing power consumption during chip testing is becoming a bottleneck for chip production and testing.Prior work has mainly focused on reducing the power dissipation in either the shift cycle or the capture cycle with little work on reducing the peak power for both the shift and capture cycles at the same time.Moreover,there has been no work on the capture power controllability.This paper presents a power-aware scan segment architecture which controls the power during the shift and capture cycles at the same time with small area overhead.Meanwhile,the dependency checking and scan segment partitioning algorithms directly reduce the switching activity of flip-flops by iteratively optimizing the scan segment grouping.This method analyzes the power controllability in terms of both the structure dependency and the clock tree impact.Tests on reference circuits ISCAS89 and IWLS2005verify the effectiveness of this architecture.