基于低阈值单元的高性能低功耗设计方法

A design method using low-threshold cell for high performance and low power consumption

在高性能IC设计中对高低两种阈值电压技术进行比较,利用低阈值电压降低动态功耗的手段实现降低总功耗的目标,并分析出了两种阈值电压低功耗设计各自适应的电路类型。首先对40nm工艺中标准单元的内部功耗、时序、尺寸进行分析。接着在相同延时下对高阈值和低阈值两种标准单元所设计的反相器链时序电路的功耗进行对比分析。最后基于Benchmark和AES两种类型电路,分别采用高阈值和低阈值进行综合,对比得出在相同时钟周期下更低功耗的设计所对应的阈值电压设计方式。结果显示,在相同的时钟频率下,对动态功耗占据总功耗比例极大的电路使用低阈值设计得到的功耗更低。同样,在动态功耗比例不是极大的电路中,当低阈值综合的slack为正时,以及当高阈值综合的slack为负、低阈值的slack为0时,用低阈值设计功耗更低;而当高阈值、低阈值综合的slack都为0时,用高阈值设计功耗更低。

To reduce the overall power consumption of high performance ICs, we compare the high threshold voltage technology with the low one and analyze their different applications. In order to reduce the total power consumption, we use the low threshold voltage technology to reduce the dynamic power consumption. Firstly, we analyze internal power consumption, timing and size of standard cells in the 40nm technology. Under the same delays we then compare the power consumption of the two kinds of inverter chains composed by standard cells with the two thresholds, respectively. We also analyze the dynamic power consumption of the benchmark and AES circuits which are synthesized by high threshold voltage and low threshold voltage respectively. By comparison, we find out the corresponding threshold voltage design approach for lower power design under the same clock cycle. The synthesis results show that for the circuits with a large ratio of dynamic power consumption to the total power consumption , low threshold voltage design can reduce power consumption; while the ratio of dynamic power consump- tion is not large, if the low threshold synthesis slack is positive or the high threshold synthesis slack is negative and the low threshold synthesis slack is zero, a low threshold voltage design can reduce power consumption; or when both of their synthesis slacks are zero, a high threshold voltage design can a- chieve lower power consumption.