期刊文献+

底充胶叠层PBGA无铅焊点随机振动应力应变分析 被引量:7

Stress and strain distribution of PBGA stacked lead-free solder joints with underfill with random vibration
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摘要 建立了底充胶叠层塑料球栅阵列(plastic ball grid array,PBGA)无铅焊点三维有限元分析模型,研究了PBGA结构方式、焊点材料、底充胶弹性模量和密度对叠层无铅焊点随机振动应力应变的影响.结果表明,底充胶可有效降低焊点内的随机振动应力应变;在其它条件相同下,对于Sn95.5Ag3.8Cu0.7,Sn96.5Ag3Cu0.5,Sn-3.5Ag和Sn63Pb37这四种焊料,采用Sn-3.5Ag的底充胶叠层焊点内的随机振动最大应力应变最小,采用Sn96.5Ag3Cu 0.5的焊点内的最大应力应变最大;随着底充胶弹性模量的增大,叠层无铅内的随机振动应力应变值相应减小;随着底充胶密度的增大,叠层无铅内的随机振动应力应变值相应增大. The 3D finite element analysis model of plastic ball grid array( PBGA) stacked lead-free solder joints with underfills was developed. By using ANSYS the finite element analysis was performed based on the model with random vibration.The influences of PBGA assembly structure,solder joint material,underfill elastic modulus and underfill density on PBGA stacked lead-free solder joint stress and strain under random vibration load were respectively studied. The results show that comparing to the no-underfill stacked solder joints the stress and strain in the stacked solder joint can be effectively reduced under random vibration load. When other conditions being equal,forSn95. 5Ag3. 8Cu0. 7, Sn96. 5Ag3Cu0. 5, Sn-3. 5Ag and Sn63Pb37,the lead free Sn-3. 5Ag stack solder joint has the minimum stress and strain while the lead-free SAC305 stack solder joint has the maximum stress and strain in the solder ball.The stress and strain in the lead-free stacked solder was reduced with the increase of underfill elasticity modulus. With the increase of the underfill density, the stress and strain in the stacked lead-free solder joint increased correspondingly.
出处 《焊接学报》 EI CAS CSCD 北大核心 2015年第10期33-36,114-115,共4页 Transactions of The China Welding Institution
基金 国家自然科学基金资助项目(51465012) 广西壮族自治区自然科学基金资助项目(2013GXNSFAA019322 2015GXNSFCA139006)
关键词 叠层无铅焊点 底充胶 随机振动 有限元分析 应力应变 stacked lead-free solder joint underfill random vibration finite element analysis stress and strain
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参考文献8

  • 1叶焕,薛松柏,张亮,王慧.CSP器件无铅焊点可靠性的有限元分析[J].焊接学报,2009,30(11):93-96. 被引量:6
  • 2张亮,薛松柏,韩宗杰,卢方焱,禹胜林,赖忠民.FCBGA器件SnAgCu焊点疲劳寿命预测[J].焊接学报,2008,29(7):85-88. 被引量:12
  • 3Kathy Wei Yan, R Wayne Johnson. Double bump flip-chip assem- bly[J]. IEEE Transactions on Electronics Packaging Manufactur- ing, 2006, 29(2) : 119 -133.
  • 4韦何耕,黄春跃,梁颖,李天明,吴松,郭广阔.热循环加载条件下PBGA叠层无铅焊点可靠性分析[J].焊接学报,2013,34(10):91-94. 被引量:27
  • 5Ong J M G, Tay A A O, Zhang X, et al. Optimization of the ther- momechanical reliability of a 65 nm Cu/low-k large-die flip chip package [ J ]. IEEE Transactions on Components and Packaging Technologies, 2009, 32(4) : 838 - 848.
  • 6郭强,赵玫,孟光.随机振动条件下SMT焊点半经验疲劳寿命累积模型[J].振动与冲击,2005,24(2):24-26. 被引量:13
  • 7Edward S Ibea, Karl I Eoha, Jing-en Luan, et al. Effect of un- filled underfills on drop impact reliability performance of area array packages [ A ]. Proceedings of IEEE 56th Electronic Components and Technology Conference [ C ]// Piscataway: Institute of Electri- cal and Electronics Engineers Inc. , 2006. 462 -466.
  • 8Alfredo Genovese, Fulvio Fontana, Mario Cesana, et al. Solder extrusions and underfill delaminations: a remarkable flip chip qualification experience[J]. The International Journal of Microcir- cuits and Electronic Packaging, 2001,24( 1 ) : 53 -60.

二级参考文献32

  • 1张启运.无铅钎焊的困惑、出路和前景[J].焊接,2007(2):6-10. 被引量:21
  • 2Amagai M, Sanko H, Maeda T, et al. Development of chip scaleter package for cen pad devices[ C]// Proceedings of the 47th IEEE Electronic Components Technology Conference, San Jose, USA, 1997:664 - 670.
  • 3Amagai M. Chip scale package (CSP) solder joint reliability and modeling [J]. Microelectronics Reliability, 1999, 39(4) : 463 - 447.
  • 4Tee T Y, Ng H S, Zhong Z W. Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA [J]. Microelectronics Reliability, 2006, 46(12): 2131- 2138.
  • 5Li X Y, Wang Z S. Thermo-fatigue life evaluation of SnAgCu solder joints in flip chip assemblies [ J ]. Materials Processing Technology, 2007, 183(1): 6- 12.
  • 6Wu J D, Ho S H, etc. Board level reliability of a stacked CSP subjected to cyclic bending [J],Microelectronic Reliability, 42 (2002),407-416
  • 7Tong Yan Tee, Hun Shen Ng, etc. Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication application [J], Microelectronics Reliability, (43)2003,1117-1123
  • 8Amagai M. Chip Scale Package(CSP)solder joint reliability and modeling [J], Microelectronics Reliability,(39) 1999,463-477
  • 9Tong Yan Tee, Hun Shen Ng, etc. Comprehensive board-level solder joint reliability modeling and testing of QFN and Power QFN Packages [J], Microelectronics Reliability,(43) 2003, 1329-1338
  • 10Dave S .Steinberg, Vibration Analysis for Electronic Equipment [M],Second Edition ,A Wiley-Interscience Publication,JOHN WILEY & SONS, 1989

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