并行可配置浮点矩阵乘法IP核设计

A Parallel Configurable Floating- point Matrix Multiplier IP Core Design

矩阵乘法是信息处理领域的常见计算,该文设计并实现了一个可自由配置的浮点矩阵乘法IP核,可满足不同计算场合的需求。该IP核采用并行结构设计,使用AXI接口,可通过参数配置实现任意维矩阵乘法,并在嵌入式系统设计中灵活调用,在Xilinx 7系列芯片的FPGA平台上进行验证了。实验结果证明了该浮点矩阵乘法IP核相对于传统乘法器设计具有计算速度快、移植性能好、资源利用少等特点。

Matrix multiplication is frequently used in the field of information processing. A configurable floating- point matrix multiplier IP core is proposed and implemented in this paper to meet different calculation requirements. This IP core is designed in parallel structure with AXI protocol. It can realize arbitrary dimension matrix multiplication through the configuration of parameters and suits well in the embedded system design. The IP core is verified on the Xilinx 7- Series FPGA platform. The experimental results showed that compared with traditional matrix multiplications,the floating- point matrix multiplier IP core design have many advantages,such as high computing speed,great portability,and less resource utilization.