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可满足性求解方法在SoC验证和测试中的应用

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摘要 介绍可满足性(SAT)求解方法在向量自动生成、符号模型检查和组合电路等价性检查等在电子设计自动化(Electronic Design automation,EDA)研究领域中的应用,阐述SoC芯片验证和测试采用可满足性(SAT)方法进行解决的原理.满足性(SAT)求解方法可有效地减少验证和测试所需时间,提高SoC芯片设计的效率和可靠性.
作者 孙强
机构地区 牡丹江师范学院工学院
出处 《牡丹江师范学院学报（自然科学版）》 2015年第4期25-27,共3页 Journal of Mudanjiang Normal University：Natural Sciences Edition
基金 黑龙江省高校青年学术骨干项目(1253G060)
关键词 片上系统 验证 测试 可满足性问题
分类号 O441.3 [理学—电磁学]
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参考文献20

  • 1Thomas Kropf. Introduction to Formal Hardware Verification[M]. Berlin: Springer Press,1999; 105-107.
  • 2Bryant R E. Graph-Based Algorithms for Boolean Function Manipulation[J]. IEEE Transactions on Computers, 1986,2 (10):677- 691.
  • 3Brand D. Verification of large synthesized designs[J]. Proceedings of International Conference of Computer-aided Design, Santa Clar- a, USA,1993534-537.
  • 4Moskewicz M, Madigan C, Zhao Y. Chaff: Engineering an Efficient SAT Solver[J]. Proceedings of Design Automation Conference, Las Vegas USA, 2001 : 530-535.
  • 5Kuehlmann Andreas. Equivalence Checking Using Cuts and Heaps[J]. Proceedings of Design Automation Conference, Anaheim, USA, 1997:263-268.
  • 6Goldherg E, Prasad M R. Using SAT for Combinational Equivalence Checking[J]. Proceedings of Design Automation Test Con- ference in Europe, Amsterdam, the Netherlands, 2001 : 114-121.
  • 7Gupta Aarti, Ganai Malay, Wang Chao, Yang Zijiang, Ashar Pranav. Learning from BDDs in SAT-based Bounded Model Checking [J]. Proceedings of ACM/IEEE Design Automation Conference, California, USA,2003 288-829.
  • 8Lu Feng, Wang Li-C, Cheng K-T, Huang Ric C-Y. A Circuit SAT Solver with Signal Correlation Guided Learning[J]. Proceedings of Design Automation b- Test Conference in Europe, Paris,France,2003: 892-897.
  • 9Lu Feng, Wang Li-C, Cheng Kwang-Ting, Moondanos John, Hanna Ziyad. A Signal Correlation Guided ATPG Solver And Its Ap- plications For Solving Difficult Industrial Cases[J]. Proceedings of Design Automation Conference, California, USA,2003,436-441.
  • 10Arora Rajat, Hsiao Michael S. Enhancing SAT-based Equivalence Checking with Static Logic Implications[J]. Proceedings of IEEE International High Level Design Validation and Test Workshop, New York, USA, 2003 : 12-14.

二级参考文献25

  • 1Kropf Thomas. Introduction to Formal Hardware Verification[M]. Springer Press, 1999.
  • 2Bryant R E. Graph-Based Algorithms for Boolean Function Manipulation[J]. IEEE Trans. Computers, 1986, C-35: 677-691.
  • 3Brand D. Verification of large synthesized designs[A]. ICCAD[C]. 1993. 534-537.
  • 4Moskewicz M, Madigan C, Zhao Y, Zhang L, Malik S. Chaff: Engineering an Efficient SAT Solver[A]. DAC[C]. 2001. 530-535.
  • 5Kuehlmann Andreas, Krohm Florian. Equivalence Checking Using Cuts and Heaps[A]. DAC[C]. 1997. 263-268.
  • 6Goldberg E, Prasad M R, Brayton R K. Using SAT for Combinational Equivalence Checking[A]. DATE[C]. 2001. 114-121.
  • 7Gupta Aarti, Ganai Malay, Wang Chao, Yang Zijiang, Ashar Pranav. Learning from BDDs in SAT-based Bounded Model Checking[A]. In proc, ACM/IEEE Design Automation Conference[C]. 2003. 288-829.
  • 8Lu Feng, Wang Li-C, Cheng K-T, Huang Ric C-Y. A Circuit SAT Solver with Signal Correlation Guided Learning[A]. Proc. Design Automation & Test Conference in Europe[C]. 2003-03. 892-897.
  • 9Lu Feng, Wang Li-C, Cheng Kwang-Ting, Moondanos John, Hanna Ziyad. A Signal Correlation Guided ATPG Solver And Its Applications For Solving Difficult Industrial Cases[A]. In Proc. Design Automation Conference[C]. 2003-06. 436-441.
  • 10Arora Rajat, Hsiao Michael S. Enhancing SAT-based Equivalence Checking with Static Logic Implications[A]. proc. IEEE International High Level Design Validation and Test Workshop[C]. 2003-11. 12-14.

共引文献6

牡丹江师范学院学报（自然科学版）
2015年 第4期

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