数字下变频中抽取滤波器的设计及FPGA实现

Design and FPGA implementation of decimation filter in DDC

针对软件无线电接收机数字下变频中高速数字信号的降采样需求,利用半带滤波器及级联积分梳状滤波器,设计了一种半带滤波器前置的多级抽取滤波器架构。通过Simulink搭建系统模型验证之后,利用Xilinx ISE 12.3在Xilinx xc5vsx95t-2ff1136 FPGA上实现了一种下采样率为64的抽取滤波器。Modelsim仿真结果表明,该抽取滤波器设计是有效的,达到了设计指标。

A structure of multistage decimation filter with half-band filter preposed was designed taking advantages of half-band fil- ter（HBF） and cascaded integrator-comb filter, for satisfying down sampling demands of high-speed digital signal in digital down conversion of software defined radio receivers. A decimation filter with down sampling ratio of 64 was implemented on Xilinx xc5vsx95t-2ff1136 FPGA using Xilinx design suite 12.3 after verifying by building system model utilizing Simulink. Simulation re- suits of Modelsim SE 6.5 proved that the design was efficient and that the designed goals were achieved.