一种高增益多级运算放大器的设计

Design of a High Gain Multistage Operational Amplifier

为了保证运算放大器在深亚微米量级也能提供足够的增益,三级运算放大器的研究成为近年的热点内容。基于SMIC 0.18μm工艺设计了一种三级运算放大器,前两级采用折叠共源共栅结构,在提供足够直流增益的同时增加了输入输出摆幅,并且采用DFCFC补偿方案使整体性能得到优化。在3.3V电源电压下,负载为5pF电容时,直流开环增益为155dB,单位增益带宽达到了32 MHz,相位裕度为56.09°。仿真结果表明,设计的三级运算放大器具有较理想的频率响应和瞬态响应,并且所需的补偿电容值较小,芯片面积得到优化,较容易在CMOS工艺下实现。

For ensuring that an operational amplifier has an adequate gain in deep submicro node, the researches on the three stage operational amplifiers became popular in recent years. A kind of three stage operational amplifier was designed based on SMIC 0.18 μm CMOS technology. The first two stages of the amplifier was in folded cascode structure, which provided enough dc gain and increased the input and output swings. The whole performance was optimized with the DFCFC compensation scheme. With a supply voltage of 3.3 V and a capacitive load of 5 pF, the amplifier featured 155 dB open-loop dc gain, 32 MHz unity gain-bandwidth and 56.09°phase margin. The simulation results indicated that the amplifier had ideal frequency response and transient response. It needed smaller compensated capacitor with the benefit of decreased die area, which was easily implemented in current CMOS technology.